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ICCD
1997
IEEE
90views Hardware» more  ICCD 1997»
14 years 1 months ago
TITAC-2: An asynchronous 32-bit microprocessor based on Scalable-Delay-Insensitive model
Asynchronous design has a potential of solving many difficulties, such as clock skew and power consumption, which synchronous counterpart suffers with current and future VLSI tech...
Akihiro Takamura, Masashi Kuwako, Masashi Imai, Ta...
SPDP
1991
IEEE
14 years 1 months ago
Local vs. global memory in the IBM RP3: experiments and performance modelling
A number of experiments regarding the placement of instructions, private data and shared data in the Non-Uniform-Memory-Access multiprocessor, RP3 has been performed. Three Scient...
Mats Brorsson
ACSC
2004
IEEE
14 years 1 months ago
Learning Models for English Speech Recognition
This paper reports on an experiment to determine the optimal parameters for a speech recogniser that is part of a computer aided instruction system for assisting learners of Engli...
Huayang Xie, Peter Andreae, Mengjie Zhang, Paul Wa...
FAC
2000
124views more  FAC 2000»
13 years 9 months ago
Algebraic Models of Correctness for Microprocessors
In this paper we present a method of describing microprocessors at different levels of temporal and data abstraction. We consider microprogrammed, pipelined and superscalar proces...
Anthony C. J. Fox, Neal A. Harman
ISVLSI
2007
IEEE
131views VLSI» more  ISVLSI 2007»
14 years 4 months ago
Improving the Quality of Bounded Model Checking by Means of Coverage Estimation
Formal verification has become an important step in circuit and system design. A prominent technique is Bounded Model Checking (BMC) which is widely used in industry. In BMC it i...
Ulrich Kühne, Daniel Große, Rolf Drechs...