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» Models of Computation for Networks on Chip
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LCN
2008
IEEE
14 years 3 months ago
Modeling of multi-resolution active network measurement time-series
Abstract—Active measurements on network paths provide endto-end network health status in terms of metrics such as bandwidth, delay, jitter and loss. Hence, they are increasingly ...
Prasad Calyam, Ananth Devulapalli
DSN
2006
IEEE
14 years 3 months ago
Automatic Instruction-Level Software-Only Recovery
As chip densities and clock rates increase, processors are becoming more susceptible to transient faults that can affect program correctness. Computer architects have typically ad...
Jonathan Chang, George A. Reis, David I. August
CASES
2008
ACM
13 years 11 months ago
Efficiency and scalability of barrier synchronization on NoC based many-core architectures
Interconnects based on Networks-on-Chip are an appealing solution to address future microprocessor designs where, very likely, hundreds of cores will be connected on a single chip...
Oreste Villa, Gianluca Palermo, Cristina Silvano
RECOMB
2003
Springer
14 years 9 months ago
Optimizing exact genetic linkage computations
Genetic linkage analysis is a challenging application which requires Bayesian networks consisting of thousands of vertices. Consequently, computing the likelihood of data, which i...
Dan Geiger, Maáyan Fishelson
ICNP
1998
IEEE
14 years 1 months ago
On Reducing the Processing Cost of On-Demand QoS Path Computation
Quality of Service (QoS) routing algorithms have become the focus of recent research due to their potential for increasing the utilization of an Integrated Services Packet Network...
George Apostolopoulos, Satish K. Tripathi