6229 search results - page 242 / 1246 » Models of Computation for Networks on Chip |
145
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ICS
2005
Tsinghua U.
15 years 10 months ago
2005
Tsinghua U.
We propose an organization for the on-chip memory system of a chip multiprocessor, in which 16 processors share a 16MB pool of 256 L2 cache banks. The L2 cache is organized as a n...
114
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ICRA
2003
IEEE
15 years 10 months ago
2003
IEEE
The forms of communication available now are categorized into the one or three dimensional. One dimensional communication includes metal wires and optical fibers in which the elec...
160
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IPPS
2003
IEEE
15 years 10 months ago
2003
IEEE
ShareStreams (Scalable Hardware Architectures for Stream Schedulers) is a canonical architecture for realizing a range of scheduling disciplines. This paper discusses the design c...
147
Voted
HOTI
2002
IEEE
15 years 9 months ago
2002
IEEE
We present an architecture and hardware for scheduling gigabit packet streams in server clusters that combines a Network Processor datapath and an FPGA for use in server NICs and ...
130
Voted
GRC
2005
IEEE
15 years 10 months ago
2005
IEEE
In this paper, we propose a linear control model for gene intervention in a genetic regulatory network. At each time step, finite controls are allowed to drive the network states...