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» Models of Computation for Networks on Chip
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ASAP
2006
IEEE
130views Hardware» more  ASAP 2006»
14 years 2 months ago
Cross Layer Design to Multi-thread a Data-Pipelining Application on a Multi-processor on Chip
Data-Pipelining is a widely used model to represent streaming applications. Incremental decomposition and optimization of a data-pipelining application onto a multi-processor plat...
Bo-Cheng Charles Lai, Patrick Schaumont, Wei Qin, ...
BMCBI
2011
13 years 3 months ago
The dChip survival analysis module for microarray data
Background: Genome-wide expression signatures are emerging as potential marker for overall survival and disease recurrence risk as evidenced by recent commercialization of gene ex...
Samir B. Amin, Parantu K. Shah, Aimin Yan, Sophia ...
BMCBI
2010
175views more  BMCBI 2010»
13 years 9 months ago
Towards high performance computing for molecular structure prediction using IBM Cell Broadband Engine - an implementation perspe
Background: RNA structure prediction problem is a computationally complex task, especially with pseudo-knots. The problem is well-studied in existing literature and predominantly ...
S. P. T. Krishnan, Sim Sze Liang, Bharadwaj Veerav...
CHI
2009
ACM
14 years 9 months ago
A personalized walk through the museum: the CHIP interactive tour guide
More and more museums aim at enhancing their visitors' museum experiences in a personalized, intensive and engaging way inside the museum. The CHIP1 (Cultural Heritage Inform...
Ivo Roes, Natalia Stash, Yiwen Wang, Lora Aroyo
ISCA
2007
IEEE
161views Hardware» more  ISCA 2007»
14 years 3 months ago
Physical simulation for animation and visual effects: parallelization and characterization for chip multiprocessors
We explore the emerging application area of physics-based simulation for computer animation and visual special effects. In particular, we examine its parallelization potential and...
Christopher J. Hughes, Radek Grzeszczuk, Eftychios...