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» Models of Computation for Networks on Chip
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ENTCS
2008
134views more  ENTCS 2008»
13 years 9 months ago
A Stack-Slicing Algorithm for Multi-Core Model Checking
The broad availability of multi-core chips on standard desktop PCs provides strong motivation for the development of new algorithms for logic model checkers that can take advantag...
Gerard J. Holzmann
BDA
2003
13 years 10 months ago
Memory Requirements for Query Execution in Highly Constrained Devices
Pervasive computing introduces data management requirements that must be tackled in a growingvariety of lightweight computing devices. Personal folders on chip, networks of sensor...
Nicolas Anciaux, Luc Bouganim, Philippe Pucheral
SAC
2010
ACM
14 years 3 months ago
Gray networking: a step towards next generation computer networks
Modern networks are very complex. It is highly desirable to reduce management complexity in next generation network design. Researchers have been seeking inspiration in natural ob...
Piyush Harsh, Randy Chow, Richard Newman
HPCA
2009
IEEE
14 years 9 months ago
Optimizing communication and capacity in a 3D stacked reconfigurable cache hierarchy
Cache hierarchies in future many-core processors are expected to grow in size and contribute a large fraction of overall processor power and performance. In this paper, we postula...
Niti Madan, Li Zhao, Naveen Muralimanohar, Anirudd...