6229 search results - page 64 / 1246 » Models of Computation for Networks on Chip |
IPPS
2010
IEEE
13 years 6 months ago
2010
IEEE
Abstract--Power density and heat density of multicore processor system are increasing exponentially with Moore's Law. High temperature on chip greatly affects its reliability,...
ESANN
2008
13 years 10 months ago
2008
We present a computational model of amygdala neural networks. It is used to simulate neuronal activation in amygdala nuclei at different stages of aversive conditioning experiments...
EWSN
2009
Springer
14 years 9 months ago
2009
Springer
As many radio chips used in today's sensor mote hardware can work at different frequencies, several multi-channel communication protocols have recently been proposed to improv...
QEST
2007
IEEE
14 years 3 months ago
2007
IEEE
Previous studies have shown that buffering packets in DRAM is a performance bottleneck. In order to understand the impediments in accessing the DRAM, we developed a detailed Petri...
GEOS
2007
Springer
14 years 3 months ago
2007
Springer
Spatio-temporal network is defined by a set of nodes, and a set of edges, where the properties of nodes and edges may vary over time. Such networks are encountered in a variety of...