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» Models of Computation for Networks on Chip
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105
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NOCS
2008
IEEE
15 years 10 months ago
SEU-Hardened Energy Recovery Pipelined Interconnects for On-Chip Networks
Alireza Ejlali, Bashir M. Al-Hashimi
93
Voted
NOCS
2008
IEEE
15 years 10 months ago
Applying Dataflow Analysis to Dimension Buffers for Guaranteed Performance in Networks on Chip
Andreas Hansson, Maarten Wiggers, Arno Moonen, Kee...
103
Voted
NOCS
2008
IEEE
15 years 10 months ago
Physical Implementation of the DSPIN Network-on-Chip in the FAUST Architecture
Ivan Miro Panades, Fabien Clermidy, Pascal Vivet, ...
98
Voted
NOCS
2008
IEEE
15 years 10 months ago
Impact of Process and Temperature Variations on Network-on-Chip Design Exploration
Bin Li, Li-Shiuan Peh, Priyadarsan Patra
110
Voted
FCCM
2007
IEEE
111views VLSI» more  FCCM 2007»
15 years 10 months ago
A Structural Object Programming Model, Architecture, Chip and Tools for Reconfigurable Computing
A new platform for reconfigurable computing has an object-based programming model, with architecture, silicon and tools designed to faithfully realize this model. The platform is ...
Michael Butts, Anthony Mark Jones, Paul Wasson