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» Modular verification of code with SAT
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TSE
2008
107views more  TSE 2008»
13 years 7 months ago
Interface Grammars for Modular Software Model Checking
We propose an interface specification language based on grammars for modular software model checking. In our interface specification language, component interfaces are specified a...
Graham Hughes, Tevfik Bultan
IFIP
2001
Springer
14 years 1 days ago
Functional Test Generation using Constraint Logic Programming
— Semi-formal verification based on symbolic simulation offers a good compromise between formal model checking and numerical simulation. The generation of functional test vector...
Zhihong Zeng, Maciej J. Ciesielski, Bruno Rouzeyre
INFSOF
2006
158views more  INFSOF 2006»
13 years 7 months ago
DEVSpecL: DEVS specification language for modeling, simulation and analysis of discrete event systems
Discrete EVent Systems Specification (DEVS) formalism supports specification of discrete event models in a hierarchical modular manner. This paper proposes a DEVS modeling languag...
Ki Jung Hong, Tag Gon Kim
JLP
2010
142views more  JLP 2010»
13 years 2 months ago
Relational bytecode correlations
We present a calculus for tracking equality relationships between values through pairs of bytecode programs. The calculus may serve as a certification mechanism for noninterferenc...
Lennart Beringer
SIGSOFT
2003
ACM
14 years 8 months ago
Towards scalable compositional analysis by refactoring design models
Automated finite-state verification techniques have matured considerably in the past several years, but state-space explosion remains an obstacle to their use. Theoretical lower b...
Yung-Pin Cheng, Michal Young, Che-Ling Huang, Chia...