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» Modularity Analysis of Logical Design Models
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EMSOFT
2007
Springer
14 years 3 months ago
Buffer optimization and dispatching scheme for embedded systems with behavioral transparency
Software components are modular and can enable post-deployment update, but their high overhead in runtime and memory is prohibitive for many embedded systems. This paper proposes ...
Jiwon Hahn, Pai H. Chou
AADEBUG
2000
Springer
14 years 1 months ago
Value Withdrawal Explanation in CSP
This work is devoted to constraint solving motivated by the debugging of constraint logic programs a la GNU-Prolog. The paper focuses only on the constraints. In this framework, c...
Gérard Ferrand, Willy Lesaint, Alexandre Te...
DAC
2005
ACM
14 years 9 months ago
Simulation models for side-channel information leaks
Small, embedded integrated circuits (ICs) such as smart cards are vulnerable to so-called side-channel attacks (SCAs). The attacker can gain information by monitoring the power co...
Kris Tiri, Ingrid Verbauwhede
DOCENG
2008
ACM
13 years 10 months ago
Improving query performance on XML documents: a workload-driven design approach
As XML has emerged as a data representation format and as great quantities of data have been stored in the XML format, XML document design has become an important and evident issu...
Rebeca Schroeder, Ronaldo dos Santos Mello
RV
2010
Springer
220views Hardware» more  RV 2010»
13 years 6 months ago
Runtime Verification with the RV System
The RV system is the first system to merge the benefits of Runtime Monitoring with Predictive Analysis. The Runtime Monitoring portion of RV is based on the successful Monitoring O...
Patrick O'Neil Meredith, Grigore Rosu