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ISCA
2012
IEEE
243views Hardware» more  ISCA 2012»
11 years 11 months ago
BlockChop: Dynamic squash elimination for hybrid processor architecture
Hybrid processors are HW/SW co-designed processors that leverage blocked-execution, the execution of regions of instructions as atomic blocks, to facilitate aggressive speculative...
Jason Mars, Naveen Kumar
ISCA
2012
IEEE
320views Hardware» more  ISCA 2012»
11 years 11 months ago
Viper: Virtual pipelines for enhanced reliability
The reliability of future processors is threatened by decreasing transistor robustness. Current architectures focus on delivering high performance at low cost; lifetime device rel...
Andrea Pellegrini, Joseph L. Greathouse, Valeria B...
ISCA
2012
IEEE
243views Hardware» more  ISCA 2012»
11 years 11 months ago
Lane decoupling for improving the timing-error resiliency of wide-SIMD architectures
A significant portion of the energy dissipated in modern integrated circuits is consumed by the overhead associated with timing guardbands that ensure reliable execution. Timing ...
Evgeni Krimer, Patrick Chiang, Mattan Erez
TVCG
2012
191views Hardware» more  TVCG 2012»
11 years 11 months ago
Facial Performance Transfer via Deformable Models and Parametric Correspondence
—The issue of transferring facial performance from one person’s face to another’s has been an area of interest for the movie industry and the computer graphics community for ...
Akshay Asthana, Miles de la Hunty, Abhinav Dhall, ...
IJCV
2012
11 years 11 months ago
Harmony Potentials - Fusing Global and Local Scale for Semantic Image Segmentation
The Hierarchical Conditional Random Field (HCRF) model have been successfully applied to a number of image labeling problems, including image segmentation. However, existing HCRF m...
Xavier Boix, Josep M. Gonfaus, Joost van de Weijer...
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