377 search results - page 19 / 76 » Multiple Instruction Stream Processor |
CJ
2006
13 years 7 months ago
2006
Most microprocessor chips today use an out-of-order instruction execution mechanism. This mechanism allows superscalar processors to extract reasonably high levels of instruction ...
PPSC
1997
13 years 9 months ago
1997
Sparse matrix-vector multiplication is an important kernel that often runs inefficiently on superscalar RISC processors. This paper describes techniques that increase instruction-...
FPL
2006
Springer
13 years 11 months ago
2006
Springer
This paper presents an implementation of a high-performance network application layer parser in FPGAs. At the core of the architecture resides a pattern matcher and a parser. The ...
ESTIMEDIA
2009
Springer
14 years 2 months ago
2009
Springer
—Real-time encoding of high-definition H.264 video is a challenge to current embedded programmable processors. Emerging stream processing methods supported by most GPUs and progr...
SIPS
2008
IEEE
14 years 2 months ago
2008
IEEE
The development of embedded system has been toward the multicore architectures in the recent years. It raises concerns in the community of supporting programming models and langua...