377 search results - page 25 / 76 » Multiple Instruction Stream Processor |
EDCC
1994
Springer
13 years 11 months ago
1994
Springer
A new control flow checking scheme, based on assigned-signature checking by a watchdog processor, is presented. This scheme is suitable for a multitasking, multiprocessor environme...
CF
2005
ACM
13 years 9 months ago
2005
ACM
In modern superscalar processors, the complex instruction scheduler could form the critical path of the pipeline stages and limit the clock cycle time. In addition, complex schedu...
PDCN
2007
13 years 9 months ago
2007
This paper describes the design and evaluation of an auto-memoization processor. The major point of this proposal is to detect the multilevel functions and loops with no additiona...
ICCD
2004
IEEE
14 years 4 months ago
2004
IEEE
In many workloads, 25% to 50% of instructions have slack allowing them to be delayed without impacting performance. To exploit this slack, processors may implement more power-efï¬...
ICDE
2006
IEEE
14 years 1 months ago
2006
IEEE
In this paper we introduce a new architectural design of a large scale distributed stream processing system. The system adopts a two layer architecture. Based on the locality and ...