377 search results - page 2 / 76 » Multiple Instruction Stream Processor |
IEEEPACT
2005
IEEE
14 years 1 months ago
2005
IEEE
VLIW architectures are popular in embedded systems because they offer high-performance processing at low cost and energy. The major problem with traditional VLIW designs is that t...
MICRO
1994
IEEE
13 years 11 months ago
1994
IEEE
Multiple issue of instructions occurs in superscalar and VLIW machines. This paper investigates a third type of machine design, which combines the advantages of code compatibility...
MICRO
1996
IEEE
13 years 11 months ago
1996
IEEE
As the issue widthof superscalar processors is increased, instructionfetch bandwidthrequirements will also increase. It will become necessary to fetch multiple basic blocks per cy...
IPPS
2005
IEEE
14 years 1 months ago
2005
IEEE
Parallel random access memory, or PRAM, is a now venerable model of parallel computation that that still retains its usefulness for the design and analysis of parallel algorithms....
ISCA
2002
IEEE
14 years 17 days ago
2002
IEEE
An instruction set architecture (ISA) suitable for future microprocessor design constraints is proposed. The ISA has hierarchical register files with a small number of accumulator...