1732 search results - page 163 / 347 » New Challenges in Parallel Optimization |
TCAD
2002
13 years 8 months ago
2002
With the advent of system-on-a-chip design, many application specific integrated circuits (ASICs) now require multiple design clocks that operate asynchronously to each other. This...
DAC
2005
ACM
14 years 9 months ago
2005
ACM
We present a new methodology which takes into consideration the effect of Within-Die (WID) process variations on a low-voltage parallel system. We show that in the presence of pro...
IPPS
2008
IEEE
14 years 2 months ago
2008
IEEE
High performance computing is critical for financial markets where analysts seek to accelerate complex optimizations such as pricing engines to maintain a competitive edge. In th...
MICRO
2003
IEEE
14 years 1 months ago
2003
IEEE
Attacking bottlenecks in modern processors is difficult because many microarchitectural events overlap with each other. This parallelism makes it difficult to both (a) assign a ...
IPPS
2002
IEEE
14 years 1 months ago
2002
IEEE
The size and complexity of current custom VLSI have forced the use of high-level programming languages to describe hardware, and compiler and synthesis technology bstract designs ...