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ISPD
2012
ACM
12 years 4 months ago
2012
ACM
Gate sizing in VLSI design is a widely-used method for power or area recovery subject to timing constraints. Several previous works have proposed gate sizing heuristics for power ...
IJCNN
2006
IEEE
14 years 2 months ago
2006
IEEE
— Job-shop scheduling is one of the most difficult production scheduling problems in industry. This paper proposes an adaptive neural network and local search hybrid approach fo...
CF
2009
ACM
14 years 3 months ago
2009
ACM
Recently, multi-core architectures with alternative memory subsystem designs have emerged. Instead of using hardwaremanaged cache hierarchies, they employ software-managed embedde...
ICCS
2007
Springer
14 years 2 months ago
2007
Springer
This paper discusses and compares several policies to place replicas in tree networks, subject to server capacity and QoS constraints. The client requests are known beforehand, wh...
CCGRID
2007
IEEE
14 years 15 days ago
2007
IEEE
We describe a hybrid linear programming (LP) and evolutionary algorithm (EA) based resource matcher suitable for heterogeneous grid environments. The hybrid matcher adopts the ite...