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ASPLOS
2004
ACM
14 years 25 days ago
Scalable selective re-execution for EDGE architectures
Pipeline flushes are becoming increasingly expensive in modern microprocessors with large instruction windows and deep pipelines. Selective re-execution is a technique that can r...
Rajagopalan Desikan, Simha Sethumadhavan, Doug Bur...
FPGA
2004
ACM
147views FPGA» more  FPGA 2004»
14 years 24 days ago
The SFRA: a corner-turn FPGA architecture
FPGAs normally operate at whatever clock rate is appropriate for the loaded configuration. When FPGAs are used as computational devices in a larger system, however, it is better ...
Nicholas Weaver, John R. Hauser, John Wawrzynek
AUIC
2002
IEEE
14 years 11 days ago
Evolving the Browser Towards a Standard User Interface Architecture
If current trends continue, it is likely that the web browser will become the only widely used user interface. Web applications will become the predominant software. Should this h...
Michael J. Rees
DAC
2000
ACM
14 years 8 months ago
METRICS: a system architecture for design process optimization
We describe METRICS, a system to recover design productivity via new infrastructure for design process optimization. METRICS seeks to treat system design and implementation as a s...
Stephen Fenstermaker, David George, Andrew B. Kahn...
ISCA
1999
IEEE
94views Hardware» more  ISCA 1999»
13 years 11 months ago
A Performance Comparison of Contemporary DRAM Architectures
In response to the growing gap between memory access time and processor speed, DRAM manufacturers have created several new DRAM architectures. This paper presents a simulation-bas...
Vinodh Cuppu, Bruce L. Jacob, Brian Davis, Trevor ...