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» Noise-tolerant dynamic circuit design
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ISLPED
2009
ACM
168views Hardware» more  ISLPED 2009»
14 years 2 months ago
Low power circuit design based on heterojunction tunneling transistors (HETTs)
The theoretical lower limit of subthreshold swing in MOSFETs (60 mV/decade) significantly restricts low voltage operation since it results in a low ON to OFF current ratio at low ...
Daeyeon Kim, Yoonmyung Lee, Jin Cai, Isaac Lauer, ...
INFOCOM
2006
IEEE
14 years 2 months ago
GMPLS-Based Dynamic Provisioning and Traffic Engineering of High-Capacity Ethernet Circuits in Hybrid Optical/Packet Networks
- Rapid progress in deployment of national and regional optical network infrastructures holds the promise to provide abundant, inexpensive bandwidth to scientific communities. The ...
Xi Yang, Chris Tracy, Jerry Sobieski, Tom Lehman
JSAC
2007
95views more  JSAC 2007»
13 years 8 months ago
Experiences in implementing an experimental wide-area GMPLS network
In this article, we describe our experiences in implementing an experimental wide-area GMPLS network called CHEETAH (Circuit-Switched End-to-End Transport Architecture). The key c...
Xiangfei Zhu, Xuan Zheng, Malathi Veeraraghavan
RTCSA
2005
IEEE
14 years 2 months ago
FPGA-Based Content Protection System for Embedded Consumer Electronics
We propose a new architecture for a content protection system that conceals confidential data and algorithms in an FPGA as electrical circuits. This architecture is designed for a...
Hiroyuki Yokoyama, Kenji Toda
DSN
2011
IEEE
12 years 8 months ago
Cross-layer resilience using wearout aware design flow
—As process technology shrinks devices, circuits experience accelerated wearout. Monitoring wearout will be critical for improving the efficiency of error detection and correctio...
Bardia Zandian, Murali Annavaram