24 search results - page 3 / 5 » Novel architectures for efficient (m, n) parallel counters |
ISPASS
2010
IEEE
14 years 2 months ago
2010
IEEE
—While many-core accelerator architectures, such as today’s Graphics Processing Units (GPUs), offer orders of magnitude more raw computing power than contemporary CPUs, their m...
ISCAS
2003
IEEE
14 years 1 months ago
2003
IEEE
A new vision chip, SCAMP-2, has been developed in a 0.35µm CMOS technology. In this paper, the design of the chip is presented, with particular emphasis on its readout architectu...
ICIP
2009
IEEE
14 years 8 months ago
2009
IEEE
The embedded-block coding with optimized truncation (EBCOT), which consists of a bit-plane coder (BPC) and a binary arithmetic coder (BAC), is the bottleneck in realizing a high-p...
ASPLOS
2008
ACM
13 years 9 months ago
2008
ACM
Multi-core processors, with low communication costs and high availability of execution cores, will increase the use of execution and compilation models that use short threads to e...
GLOBECOM
2008
IEEE
14 years 2 months ago
2008
IEEE
—We present a novel cost-effective multicast capable optical cross connect (MC-OXC) node architecture which improves efficiency of optical power by constraining splitting to only...