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ISCA
1995
IEEE
120views Hardware» more  ISCA 1995»
15 years 6 months ago
Streamlining Data Cache Access with Fast Address Calculation
For many programs, especially integer codes, untolerated load instruction latencies account for a significant portion of total execution time. In this paper, we present the desig...
Todd M. Austin, Dionisios N. Pnevmatikatos, Gurind...
ISCA
1995
IEEE
98views Hardware» more  ISCA 1995»
15 years 6 months ago
Instruction Fetching: Coping with Code Bloat
Previous research has shown that the SPEC benchmarks achieve low miss ratios in relatively small instruction caches. This paper presents evidence that current software-development...
Richard Uhlig, David Nagle, Trevor N. Mudge, Stuar...
CASES
2009
ACM
15 years 5 months ago
A case study of on-chip sensor network in multiprocessor system-on-chip
Reducing feature sizes and power supply voltage allows integrating more processing units (PUs) on multiprocessor system-on-chip (MPSoC) to satisfy the increasing demands of applic...
Yu Wang 0002, Jiang Xu, Shengxi Huang, Weichen Liu...
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ICDE
2010
IEEE
206views Database» more  ICDE 2010»
15 years 4 months ago
HECATAEUS: Regulating Schema Evolution
HECATAEUS is an open-source software tool for enabling impact prediction, what-if analysis, and regulation of relational database schema evolution. We follow a graph theoretic appr...
George Papastefanatos, Panos Vassiliadis, Alkis Si...
CAV
2010
Springer
239views Hardware» more  CAV 2010»
15 years 4 months ago
Universal Causality Graphs: A Precise Happens-Before Model for Detecting Bugs in Concurrent Programs
Triggering errors in concurrent programs is a notoriously difficult task. A key reason for this is the behavioral complexity resulting from the large number of interleavings of op...
Vineet Kahlon, Chao Wang
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