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ARVLSI
2001
IEEE
289views VLSI» more  ARVLSI 2001»
15 years 9 months ago
A High-Performance 64-bit Adder Implemented in Output Prediction Logic
Output Prediction Logic (OPL) is a technique that can be applied to conventional CMOS logic families to obtain considerable speedups. When applied to static CMOS, OPL retains the ...
Sheng Sun, Larry McMurchie, Carl Sechen
DAC
1995
ACM
15 years 9 months ago
Performance Analysis of Embedded Software Using Implicit Path Enumeration
—Embedded computer systems are characterized by the presence of a processor running application-specific dedicated software. A large number of these systems must satisfy real-ti...
Yau-Tsun Steven Li, Sharad Malik
156
Voted
MICRO
1995
IEEE
97views Hardware» more  MICRO 1995»
15 years 9 months ago
Improving CISC instruction decoding performance using a fill unit
Current superscalar processors, both RISC and CISC, require substantial instruction fetch and decode bandwidth to keep multiple functional units utilized. While CISC instructions ...
Mark Smotherman, Manoj Franklin
EURONGI
2008
Springer
15 years 7 months ago
Performance Evaluation of Overlay-Based Range Queries in Mobile Systems
Current mobility management systems are operator centralized, and focused on single link technologies. In heterogeneous wireless mesh networks, vertical handovers could be a length...
Amine M. Houyou, Alexander Stenzer, Hermann de Mee...
LREC
2008
104views Education» more  LREC 2008»
15 years 7 months ago
Performance Evaluation of Speech Translation Systems
One of the most challenging tasks for uniformed service personnel serving in foreign countries is effective verbal communication with the local population. To remedy this problem,...
Brian A. Weiss, Craig Schlenoff, Greg Sanders, Mic...