We have investigated the register file requirements of dynamically scheduled processors using register renaming and dispatch queues running the SPEC92 benchmarks. We looked at pro...
In the near future, semiconductor technology will allow the integration of multiple processors on a chip or multichipmodule (MCM). In this paper we investigate the architecture an...
Abstract-- We explore the performance and hardware complexity tradeoffs associated with performing iterative multipleinput multiple-output (MIMO) detection using a sphere decoder a...
Abstract— In this paper, we propose and evaluate the performance of new link layer frame transmission techniques for MIMO (multiple input multiple output) wireless systems from a...
We present an architecture of a hosting system consisting of a set of hosted Web Services subject to QoS constraints, and a certain number of servers used to run users demand. The ...