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HPCA
1996
IEEE
15 years 10 months ago
Register File Design Considerations in Dynamically Scheduled Processors
We have investigated the register file requirements of dynamically scheduled processors using register renaming and dispatch queues running the SPEC92 benchmarks. We looked at pro...
Keith I. Farkas, Norman P. Jouppi, Paul Chow
ISCA
1994
IEEE
104views Hardware» more  ISCA 1994»
15 years 10 months ago
Exploring the Design Space for a Shared-Cache Multiprocessor
In the near future, semiconductor technology will allow the integration of multiple processors on a chip or multichipmodule (MCM). In this paper we investigate the architecture an...
Basem A. Nayfeh, Kunle Olukotun
JSAC
2008
124views more  JSAC 2008»
15 years 6 months ago
Design Tradeoffs and Hardware Architecture for Real-Time Iterative MIMO Detection using Sphere Decoding and LDPC Coding
Abstract-- We explore the performance and hardware complexity tradeoffs associated with performing iterative multipleinput multiple-output (MIMO) detection using a sphere decoder a...
Hyungjin Kim, Dong-U Lee, John D. Villasenor
190
Voted
JCM
2007
156views more  JCM 2007»
15 years 5 months ago
MIMO Link Layer Transmission Techniques Based on Cross Layer Design
Abstract— In this paper, we propose and evaluate the performance of new link layer frame transmission techniques for MIMO (multiple input multiple output) wireless systems from a...
Wessam Ajib, David Haccoun, Jean-François F...
CORR
2010
Springer
163views Education» more  CORR 2010»
15 years 3 months ago
Design of QoS-aware Provisioning Systems
We present an architecture of a hosting system consisting of a set of hosted Web Services subject to QoS constraints, and a certain number of servers used to run users demand. The ...
Michele Mazzucco, Manuel Mazzara, Nicola Dragoni