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ICSM
1994
IEEE
15 years 10 months ago
An Experiment on the Effect of Design Recording on Impact Analysis
An experimental study is presented in which participants perform impact analysis on alternate forms of design record information. The primary objective of the research is to asses...
Fabio Abbattista, Filippo Lanubile, Gemma Mastello...
RTSS
1999
IEEE
15 years 10 months ago
Design and Evaluation of a Feedback Control EDF Scheduling Algorithm
Despite the significant body of results in real-time scheduling, many real world problems are not easily supported. While algorithms such as Earliest Deadline First, Rate Monotoni...
Chenyang Lu, John A. Stankovic, Gang Tao, Sang Hyu...
ECRTS
2009
IEEE
15 years 3 months ago
On the Design and Implementation of a Cache-Aware Multicore Real-Time Scheduler
Multicore architectures, which have multiple processing units on a single chip, have been adopted by most chip manufacturers. Most such chips contain on-chip caches that are share...
John M. Calandrino, James H. Anderson
TSP
2010
15 years 21 days ago
Zero-forcing DFE transceiver design over slowly time-varying MIMO channels using ST-GTD
This paper considers the optimization of transceivers with decision feedback equalizers (DFE) for slowly time-varying memoryless multi-input multi-output (MIMO) channels. The data ...
Chih-Hao Liu, Palghat P. Vaidyanathan
DAC
2010
ACM
15 years 10 months ago
Circuit modeling for practical many-core architecture design exploration
Current tools for computer architecture design lack standard support for multi- and many-core development. We propose using circuit models to describe the multiple processor archi...
Dean Truong, Bevan M. Baas