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IEICET
2007
48views more  IEICET 2007»
13 years 8 months ago
TCP-Ho: A Congestion Control Algorithm with Design and Performance Evaluation
Cheng-Yuan Ho, Yi-Cheng Chan, Yaw-Chung Chen
JISE
2007
101views more  JISE 2007»
13 years 8 months ago
Design, Implementation, and Performance Evaluation of Flash Memory-based File System on Chip
Seongjun Ahn, Jongmoo Choi, Donghee Lee, Sam H. No...
TVLSI
2008
133views more  TVLSI 2008»
13 years 8 months ago
A Medium-Grain Reconfigurable Architecture for DSP: VLSI Design, Benchmark Mapping, and Performance
Reconfigurable hardware has become a well-accepted option for implementing digital signal processing (DSP). Traditional devices such as field-programmable gate arrays offer good fi...
Mitchell J. Myjak, José G. Delgado-Frias