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TVLSI
2008
164views more  TVLSI 2008»
13 years 8 months ago
Dynamically Configurable Bus Topologies for High-Performance On-Chip Communication
The on-chip communication architecture is a major determinant of overall performance in complex System-on-Chip (SoC) designs. Since the communication requirements of SoC components...
Krishna Sekar, Kanishka Lahiri, Anand Raghunathan,...
ICDCS
2009
IEEE
13 years 6 months ago
The Case for Spam-Aware High Performance Mail Server Architecture
The email volume per mailbox has largely remained low and unchanged in the past several decades, and hence mail server performance has largely remained a secondary issue. The stee...
Abhinav Pathak, Syed Ali Raza Jafri, Y. Charlie Hu
EENERGY
2010
14 years 9 days ago
Energy saving and network performance: a trade-off approach
Power consumption of the Information and Communication Technology sector (ICT) has recently become a key challenge. In particular, actions to improve energy-efficiency of Internet...
Carla Panarello, Alfio Lombardo, Giovanni Schembra...
CODES
2008
IEEE
13 years 10 months ago
Performance debugging of Esterel specifications
Synchronous languages like Esterel have been widely adopted for designing reactive systems in safety-critical domains such as avionics. Specifications written in Esterel are based...
Lei Ju, Bach Khoa Huynh, Abhik Roychoudhury, Samar...
BMCBI
2010
175views more  BMCBI 2010»
13 years 9 months ago
Towards high performance computing for molecular structure prediction using IBM Cell Broadband Engine - an implementation perspe
Background: RNA structure prediction problem is a computationally complex task, especially with pseudo-knots. The problem is well-studied in existing literature and predominantly ...
S. P. T. Krishnan, Sim Sze Liang, Bharadwaj Veerav...