58 search results - page 7 / 12 » Oblivious Parallel RAM and Applications |
ISAAC
2007
Springer
14 years 4 months ago
2007
Springer
Abstract. We show how to represent sets in a linear space data structure such that expressions involving unions and intersections of sets can be computed in a worst-case efficient ...
DELTA
2008
IEEE
13 years 11 months ago
2008
IEEE
As semiconductor technology advances, the performance gap between processor and memory has become one of the major issues in computer design. In order to bridge this gap, many met...
CGO
2008
IEEE
14 years 4 months ago
2008
IEEE
The recent trend in the processor industry of packing multiple processor cores in a chip has increased the importance of automatic techniques for extracting thread level paralleli...
SPAA
2005
ACM
14 years 3 months ago
2005
ACM
We describe a new class of utility-maximization scheduling problem with precedence constraints, the disconnected staged scheduling problem (DSSP). DSSP is a nonpreemptive multipro...
DFT
2006
IEEE
14 years 3 months ago
2006
IEEE
This paper describes a methodology of creating a built-in diagnostic system of a System on Chip and experimental results of the system application on the AT94K FPSLIC with cores d...