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» On Constructing a Communicative Space in HRI
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SIGCOMM
1998
ACM
13 years 11 months ago
Fast and Scalable Layer Four Switching
In Layer Four switching, the route and resources allocated to a packet are determined by the destination address as well as other header elds of the packet such as source address,...
Venkatachary Srinivasan, George Varghese, Subhash ...
ANCS
2006
ACM
13 years 11 months ago
Efficient memory utilization on network processors for deep packet inspection
Deep Packet Inspection (DPI) refers to examining both packet header and payload to look for predefined patterns, which is essential for network security, intrusion detection and c...
Piti Piyachon, Yan Luo
TCOM
2008
92views more  TCOM 2008»
13 years 7 months ago
Mailbox switch: a scalable two-stage switch architecture for conflict resolution of ordered packets
Abstract-- Traditionally, conflict resolution in an inputbuffered switch is solved by finding a matching between inputs and outputs per time slot. To do this, a switch not only nee...
Cheng-Shang Chang, Duan-Shin Lee, Ying-Ju Shih, Ch...
ACMMSP
2006
ACM
252views Hardware» more  ACMMSP 2006»
14 years 1 months ago
Deconstructing process isolation
Most operating systems enforce process isolation through hardware protection mechanisms such as memory segmentation, page mapping, and differentiated user and kernel instructions....
Mark Aiken, Manuel Fähndrich, Chris Hawblitze...
CRYPTO
2001
Springer
152views Cryptology» more  CRYPTO 2001»
13 years 12 months ago
Secure Distributed Linear Algebra in a Constant Number of Rounds
Consider a network of processors among which elements in a finite field K can be verifiably shared in a constant number of rounds. Assume furthermore constant-round protocols ar...
Ronald Cramer, Ivan Damgård