Statistical static timing analysis (SSTA) is emerging as a solution for predicting the timing characteristics of digital circuits under process variability. For computing the stat...
Kaviraj Chopra, Bo Zhai, David Blaauw, Dennis Sylv...
The growing impact of within-die process variation has created the need for statistical timing analysis, where gate delays are modeled as random variables. Statistical timing anal...
Aseem Agarwal, David Blaauw, Vladimir Zolotov, Sar...
The aim of this paper is to propose tools for statistical analysis of shape families using morphological operators. Given a series of shape families (or shape categories), the appr...
— As technology scales into the sub-90nm domain, manufacturing variations become an increasingly significant portion of circuit delay. As a result, delays must be modeled as sta...
Matthew R. Guthaus, Natesan Venkateswaran, Chandu ...
A vast literature has been published on Statistical Static Timing Analysis (SSTA), its motivations, its different implementations and their runtime/accuracy trade-offs. However, v...
A. Nardi, Emre Tuncer, S. Naidu, A. Antonau, S. Gr...