287 search results - page 33 / 58 » On Exploiting Task Duplication in Parallel Program Schedulin... |
ENDM
2000
13 years 8 months ago
2000
Planning and scheduling attracts an unceasing attention of computer science community. Several research areas like Artificial Intelligence, Operations Research and Constraint Prog...
ICS
2001
Tsinghua U.
14 years 1 months ago
2001
Tsinghua U.
The issue logic of dynamically scheduled superscalar processors is one of their most complex and power-consuming parts. In this paper we present alternative issue-logic designs th...
ICASSP
2008
IEEE
14 years 3 months ago
2008
IEEE
Multiple memory banks design is employed in many high performance DSP processors. This architectural feature supports higher memory bandwidth by allowing multiple data memory acce...
ASPLOS
2009
ACM
14 years 9 months ago
2009
ACM
Parallel bit stream algorithms exploit the SWAR (SIMD within a register) capabilities of commodity processors in high-performance text processing applications such as UTF8 to UTF-...
ISPAN
2002
IEEE
14 years 1 months ago
2002
IEEE
In the directed acyclic graph (dag) model of algorithms, consider the following problem for precedence-constrained multiprocessor schedules for array computations: Given a sequenc...