826 search results - page 89 / 166 » On Local Register Allocation |
MICRO
1995
IEEE
14 years 13 days ago
1995
IEEE
Current superscalar processors, both RISC and CISC, require substantial instruction fetch and decode bandwidth to keep multiple functional units utilized. While CISC instructions ...
JVM
2004
13 years 10 months ago
2004
Tools supporting dynamic code generation tend too be low-level (leaving much work to the client application) or too intimately related with the language/system in which they are u...
AINA
2010
IEEE
13 years 9 months ago
2010
IEEE
—Virtual machines offer unique advantages to the scientific computing community, such as Quality of Service(QoS) guarantee, performance isolation, easy resource management, and ...
IJPP
2006
13 years 9 months ago
2006
Chip multiprocessors hold great promise for achieving scalability in future systems. Microthreaded chip multiprocessors add a means of exploiting legacy code in such systems. Usin...
TVLSI
2008
13 years 8 months ago
2008
Much effort in register transfer level (RTL) design has been devoted to developing "push-button" types of tools. However, given the highly complex nature, and lack of con...