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» On Modeling Cross-Talk Faults
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MEMOCODE
2007
IEEE
14 years 3 months ago
Combining Multi-Valued Logics in SAT-based ATPG for Path Delay Faults
Due to the rapidly growing speed and the decreasing size of gates in modern chips, the probability of faults caused by the production process grows. Already small variations lead ...
Stephan Eggersglüß, Görschwin Fey,...
ISVLSI
2007
IEEE
121views VLSI» more  ISVLSI 2007»
14 years 3 months ago
Performance of Graceful Degradation for Cache Faults
In sub-90nm technologies, more frequent hard faults pose a serious burden on processor design and yield control. In addition to manufacturing-time chip repair schemes, microarchit...
Hyunjin Lee, Sangyeun Cho, Bruce R. Childers
IEEEARES
2006
IEEE
14 years 2 months ago
Application of the Digraph Method in System Fault Diagnostics
There is an increasing demand for highly reliable systems in the safety conscious climate of today’s world. When a fault does occur there are two desirable outcomes. Firstly, de...
E. M. Kelly, L. M. Bartlett
ASIACRYPT
2009
Springer
14 years 1 months ago
PSS Is Secure against Random Fault Attacks
A fault attack consists in inducing hardware malfunctions in order to recover secrets from electronic devices. One of the most famous fault attack is Bellcore’s attack against RS...
Jean-Sébastien Coron, Avradip Mandal
DSN
2004
IEEE
14 years 13 days ago
Optimal Object State Transfer - Recovery Policies for Fault Tolerant Distributed Systems
Recent developments in the field of object-based fault tolerance and the advent of the first OMG FTCORBA compliant middleware raise new requirements for the design process of dist...
Panagiotis Katsaros, Constantine Lazos