We consider the problem of performance driven lookup-table (LUT) based technology mapping for FPGAs using a general delay model. In the general delay model, each interconnection e...
We study the nominal delay minimization problem in LUTbased FPGA technologymapping, where interconnect delay is assumed proportionalto net fanout size. We prove that the delay-opt...
In this paper, we study the technology mapping problem for a novel FPGA architecture that is based on k-input single-output PLA-like cells, or, k/m-macrocells. Each cell in this a...
— This paper presents Hermes, a depth-optimal LUT based FPGA mapping algorithm. The presented algorithm is based on a new strategy for finding LUTs allowing to find a good LUT ...
In this paper we study the area and depth trade-off in LUT based FPGA technology mapping. Starting from a depth-optimal mapping solution, we perform a number of depth relaxation o...