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» On Parallel Pseudo-Random Number Generation
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VLSID
2005
IEEE
124views VLSI» more  VLSID 2005»
14 years 2 months ago
Design of a Reversible Binary Coded Decimal Adder by Using Reversible 4-Bit Parallel Adder
In this paper, we have proposed a design technique for the reversible circuit of Binary Coded Decimal (BCD) adder. The proposed circuit has the ability to add two 4bits binary var...
Hafiz Md. Hasan Babu, Ahsan Raja Chowdhury
BMCBI
2010
134views more  BMCBI 2010»
13 years 8 months ago
R-Gada: a fast and flexible pipeline for copy number analysis in association studies
Background: Genome-wide association studies (GWAS) using Copy Number Variation (CNV) are becoming a central focus of genetic research. CNVs have successfully provided target genom...
Roger Pique-Regi, Alejandro Cáceres, Juan R...
BMCBI
2006
157views more  BMCBI 2006»
13 years 8 months ago
Determination of the minimum number of microarray experiments for discovery of gene expression patterns
Background: One type of DNA microarray experiment is discovery of gene expression patterns for a cell line undergoing a biological process over a series of time points. Two import...
Fang-Xiang Wu, W. J. Zhang, Anthony J. Kusalik
PDP
2007
IEEE
14 years 2 months ago
Parallel-External Computation of the Cycle Structure of Invertible Cryptographic Functions
We present an algorithm to compute the cycle structure of large directed graphs where each node has exactly one outgoing edge. Such graphs appear as state diagrams of finite stat...
Andreas Beckmann, Jorg Keller
ICPP
1998
IEEE
14 years 23 days ago
Parallel Algorithms for Airline Crew Planning on Networks of Workstations
The crew planning problem has been successfully solved on a loosely connected network of workstations (NOW) using advanced computational techniques and efficient communication pat...
Christos Goumopoulos, Panayiotis Alefragis, Efthym...