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ISCA
2012
IEEE
279views Hardware» more  ISCA 2012»
11 years 11 months ago
Staged memory scheduling: Achieving high performance and scalability in heterogeneous systems
When multiple processor (CPU) cores and a GPU integrated together on the same chip share the off-chip main memory, requests from the GPU can heavily interfere with requests from t...
Rachata Ausavarungnirun, Kevin Kai-Wei Chang, Lava...
SECON
2008
IEEE
14 years 3 months ago
On Distributed Optimization Using Peer-to-Peer Communications in Wireless Sensor Networks
—We describe and evaluate a suite of distributed and computationally efficient algorithms for solving a class of convex optimization problems in wireless sensor networks. The pr...
Björn Johansson, Cesare M. Carretti, Mikael J...
VEE
2006
ACM
150views Virtualization» more  VEE 2006»
14 years 3 months ago
Evaluating fragment construction policies for SDT systems
Software Dynamic Translation (SDT) systems have been used for program instrumentation, dynamic optimization, security policy enforcement, intrusion detection, and many other uses....
Jason Hiser, Daniel Williams, Adrian Filipi, Jack ...
VALUETOOLS
2006
ACM
167views Hardware» more  VALUETOOLS 2006»
14 years 3 months ago
Detailed cache simulation for detecting bottleneck, miss reason and optimization potentialities
Cache locality optimization is an efficient way for reducing the idle time of modern processors in waiting for needed data. This kind of optimization can be achieved either on the...
Jie Tao, Wolfgang Karl
ISCAS
2005
IEEE
127views Hardware» more  ISCAS 2005»
14 years 2 months ago
Energy and latency evaluation of NoC topologies
Abstract — Mapping applications onto different networks-onchip (NoCs) topologies is done by mapping processing cores on local ports of routers considering requirements like laten...
Márcio Eduardo Kreutz, César A. M. M...