1529 search results - page 188 / 306 » On Timing Analysis of Combinational Circuits |
FMCAD
2004
Springer
14 years 1 months ago
2004
Springer
Most symbolic model checkers are based on either Binary Decision Diagrams (BDDs), which may grow exponentially large, or Satisfiability (SAT) solvers, whose time requirements rapi...
ISPD
2003
ACM
14 years 1 months ago
2003
ACM
Traditional multilevel partitioning approaches have shown good performance with respect to cutsize, but offer no guarantees with respect to system performance. Timing-driven part...
RSP
1998
IEEE
14 years 11 days ago
1998
IEEE
A rapid design methodology for orthonormal wavelet transform cores has been developed. This methodology is based on a generic, scaleable architecture utilising time-interleaved co...
DAC
2007
ACM
14 years 1 days ago
2007
ACM
While cryptographic algorithms are usually strong against mathematical attacks, their practical implementation, both in software and in hardware, opens the door to side-channel at...
DAC
1995
ACM
13 years 11 months ago
1995
ACM
The Elmore delay is an extremely popular delay metric, particularly for RC tree analysis. The widespread usage of this metric is mainly attributable to it being the most accurate ...