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CCGRID
2001
IEEE
14 years 10 days ago
2001
IEEE
Active networks allow computations to be performed innetwork at routers as messages pass through them. Active networks offer unique opportunities to optimize networkcentric applic...
ICS
2009
Tsinghua U.
14 years 3 months ago
2009
Tsinghua U.
Iterative stencil loops (ISLs) are used in many applications and tiling is a well-known technique to localize their computation. When ISLs are tiled across a parallel architecture...
IPPS
1994
IEEE
14 years 25 days ago
1994
IEEE
A parallel transputer-based emulator has been developed to evaluate the DDM--ahighlyparallel virtual shared memory architecture. The emulator provides performance results of a har...
IEEEPACT
2007
IEEE
14 years 3 months ago
2007
IEEE
As multi-core architectures flourish in the marketplace, multi-application workload scenarios (such as server consolidation) are growing rapidly. When running multiple application...
ISPASS
2008
IEEE
2008
IEEE
An Analysis of I/O And Syscalls In Critical Sections And Their Implications For Transactional Memory
14 years 3 months ago
Transactional memory (TM) is a scalable and concurrent way to build atomic sections. One aspect of TM that remains unclear is how side-effecting operations – that is, those whic...