Sciweavers

86 search results - page 17 / 18
» On a Tighter Integration of Functional and Logic Programming
Sort
View
ICISS
2010
Springer
13 years 5 months ago
ValueGuard: Protection of Native Applications against Data-Only Buffer Overflows
Abstract. Code injection attacks that target the control-data of an application have been prevalent amongst exploit writers for over 20 years. Today however, these attacks are gett...
Steven Van Acker, Nick Nikiforakis, Pieter Philipp...
DAC
2009
ACM
14 years 2 months ago
Clock skew optimization via wiresizing for timing sign-off covering all process corners
Manufacturing process variability impacts the performance of synchronous logic circuits by means of its effect on both clock network and functional block delays. Typically, varia...
Sari Onaissi, Khaled R. Heloue, Farid N. Najm
CUZA
2002
130views more  CUZA 2002»
13 years 7 months ago
Distributed Threads in Java
In this paper we present a mechanism for serializing the execution-state of a distributed Java application that is implemented on a conventional Object Request Broker (ORB) archite...
Danny Weyns, Eddy Truyen, Pierre Verbaeten
BIOCOMP
2007
13 years 9 months ago
Stability Analysis of Genetic Regulatory Network with Additive Noises
Background: Genetic regulatory networks (GRN) can be described by differential equations with SUM logic which has been found in many natural systems. Identification of the network...
Yufang Jin
ICCAD
2006
IEEE
127views Hardware» more  ICCAD 2006»
14 years 4 months ago
Joint design-time and post-silicon minimization of parametric yield loss using adjustable robust optimization
Parametric yield loss due to variability can be effectively reduced by both design-time optimization strategies and by adjusting circuit parameters to the realizations of variable...
Murari Mani, Ashish Kumar Singh, Michael Orshansky