Sciweavers

373 search results - page 13 / 75
» On a model of three-dimensional bursting and its parallel im...
Sort
View
DATE
2006
IEEE
121views Hardware» more  DATE 2006»
14 years 2 months ago
Analysis of the impact of bus implemented EDCs on on-chip SSN
In this paper we analyze the impact of error detecting codes, implemented on an on-chip bus, on the on-chip simultaneous switching noise (SSN). First, we analyze in detail how SSN...
Daniele Rossi, Carlo Steiner, Cecilia Metra
ICDCS
2007
IEEE
14 years 3 months ago
Testing Security Properties of Protocol Implementations - a Machine Learning Based Approach
Security and reliability of network protocol implementations are essential for communication services. Most of the approaches for verifying security and reliability, such as forma...
Guoqiang Shu, David Lee
IPPS
2006
IEEE
14 years 2 months ago
Parallel genetic algorithm for SPICE model parameter extraction
Models of simulation program with integrated circuit emphasis (SPICE) are currently playing a central role in the connection between circuit design and chip fabrication communitie...
Yiming Li, Yen-Yu Cho
IJON
2006
73views more  IJON 2006»
13 years 8 months ago
Selective attention implemented with dynamic synapses and integrate-and-fire neurons
Selective attention is a process widely used by biological sensory systems to overcome the problem of limited parallel processing capacity: salient subregions of the input stimuli...
Chiara Bartolozzi, Giacomo Indiveri
PDP
2002
IEEE
14 years 1 months ago
A Parametrized Algorithm that Implements Sequential, Causal, and Cache Memory Consistency
In this paper we present an algorithm that can be used to implement sequential, causal, or cache consistency in distributed shared memory (DSM) systems. For this purpose it has a ...
Ernesto Jiménez, Antonio Fernández, ...