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ISCAS
2003
IEEE
167views Hardware» more  ISCAS 2003»
14 years 28 days ago
The multi-level paradigm for distributed fault detection in networks with unreliable processors
In this paper, we study the effectiveness of the multilevel paradigm in considerably reducing the diagnosis latency of distributed algorithms for fault detection in networks with ...
Krishnaiyan Thulasiraman, Ming-Shan Su, V. Goel
ISPD
2003
ACM
79views Hardware» more  ISPD 2003»
14 years 27 days ago
Floorplanning of pipelined array modules using sequence pairs
Floorplanning individual pipelined array modules of a larger overall die can yield beneficial results. Critical paths in every pipeline stage of a pipelined design are roughly equ...
Matthew Moe, Herman Schmit
FPL
2009
Springer
117views Hardware» more  FPL 2009»
14 years 8 days ago
Data parallel FPGA workloads: Software versus hardware
Commercial soft processors are unable to effectively exploit the data parallelism present in many embedded systems workloads, requiring FPGA designers to exploit it (laboriously) ...
Peter Yiannacouras, J. Gregory Steffan, Jonathan R...
IWDC
2001
Springer
140views Communications» more  IWDC 2001»
14 years 3 days ago
Satellite Systems Performance with TCP-IP Applications
Mobile Internet access is becoming extremely popular because users depend on the Internet for many activities in their daily routine. Satellites are well suited for mobile Interne...
Pierpaolo Loreti, Michele Luglio, Rohit Kapoor, J....
FPGA
2000
ACM
161views FPGA» more  FPGA 2000»
13 years 11 months ago
The effect of LUT and cluster size on deep-submicron FPGA performance and density
In this paper we revisit the FPGA architectural issue of the effect of logic block functionality on FPGA performance and density. In particular, in the context of lookup table, cl...
Elias Ahmed, Jonathan Rose