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ICCAD
1995
IEEE
135views Hardware» more  ICCAD 1995»
14 years 2 days ago
An iterative improvement algorithm for low power data path synthesis
We address the problem of minimizing power consumption in behavioral synthesis of data-dominated circuits. The complex nature of power as a cost function implies that the effects ...
Anand Raghunathan, Niraj K. Jha
LCTRTS
2007
Springer
14 years 2 months ago
Enabling compiler flow for embedded VLIW DSP processors with distributed register files
High-performance and low-power VLIW DSP processors are increasingly deployed on embedded devices to process video and multimedia applications. For reducing power and cost in desig...
Chung-Kai Chen, Ling-Hua Tseng, Shih-Chang Chen, Y...
HPCA
2000
IEEE
14 years 28 days ago
Flit-Reservation Flow Control
This paper presents flit-reservation flow control, in which control flits traverse the network in advance of data flits, reserving buffers and channel bandwidth. Flit-reservation ...
Li-Shiuan Peh, William J. Dally
TCSV
2008
129views more  TCSV 2008»
13 years 8 months ago
Efficient Architecture Design of Motion-Compensated Temporal Filtering/Motion Compensated Prediction Engine
Since motion-compensated temporal filtering (MCTF) becomes an important temporal prediction scheme in video coding algorithms, this paper presents an efficient temporal prediction ...
Yi-Hau Chen, Chih-Chi Cheng, Tzu-Der Chuang, Ching...
CGO
2003
IEEE
14 years 1 months ago
Dynamic Binary Translation for Accumulator-Oriented Architectures
A dynamic binary translation system for a co-designed virtual machine is described and evaluated. The underlying hardware directly executes an accumulator-oriented instruction set...
Ho-Seop Kim, James E. Smith