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» On the Architecture of System Verification Environments
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SDL
2001
125views Hardware» more  SDL 2001»
13 years 8 months ago
Verification of Quantitative Temporal Properties of SDL Specifications
Abstract. We describe an approach for the verification of quantitative temporal properties of SDL specifications, which adapts techniques developed for timed automata [2]. With res...
Iulian Ober, Alain Kerbrat
DAC
2007
ACM
13 years 11 months ago
A Framework for the Validation of Processor Architecture Compliance
We present a framework for validating the compliance of a design with a given architecture. Our approach is centered on the concept of misinterpretations. These include missing be...
Allon Adir, Sigal Asaf, Laurent Fournier, Itai Jae...
WORDS
2005
IEEE
14 years 29 days ago
Specification-Based Verification and Validation of Web Services and Service-Oriented Operating Systems
Service-Oriented Architecture (SOA) and Web Services (WS) have received significant attention recently. Even though WS are based on open standards and support software interoperab...
Wei-Tek Tsai, Yinong Chen, Raymond A. Paul
COMCOM
1998
117views more  COMCOM 1998»
13 years 7 months ago
Specification, validation, and verification of time-critical systems
In this paper, we propose a new formalism, named the Timed Communicating Finite State Machine (Timed CFSM), for specifying and verifying time-critical systems. Timed CFSM preserve...
Shiuh-Pyng Shieh, Jun-Nan Chen
BIRTHDAY
2006
Springer
13 years 11 months ago
Realistic Worst-Case Execution Time Analysis in the Context of Pervasive System Verification
We describe a gate level design of a FlexRay-like bus interface. An electronic control unit (ECU) is obtained by integrating this interface into the design of the verified VAMP pro...
Steffen Knapp, Wolfgang J. Paul