155 search results - page 7 / 31 » On the Automatic Parallelization of the Perfect Benchmarks |
ICS
2005
Tsinghua U.
14 years 1 months ago
2005
Tsinghua U.
Performance simulation tools must be validated during the design process as functional models and early hardware are developed, so that designers can be sure of the performance of...
ICS
1995
Tsinghua U.
13 years 11 months ago
1995
Tsinghua U.
Modulo scheduling is an e cient technique for exploiting instruction level parallelism in a variety of loops, resulting in high performance code but increased register requirement...
SC
1995
ACM
13 years 11 months ago
1995
ACM
This paper presents an extensive empirical evaluation of an interprocedural parallelizing compiler, developed as part of the Stanford SUIF compiler system. The system incorporates...
LCPC
1998
Springer
14 years 2 days ago
1998
Springer
: In this paper, theoretical aspects to demonstrate the accuracy of the Interval Test (the I test and the direction vector I test) to be applied for resolving the problem stated ab...
IPPS
2002
IEEE
14 years 23 days ago
2002
IEEE
This paper presents preliminary efforts to develop compilation and execution environments that achieve performance portability of multilevel parallelization on hierarchical archit...