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» On the Circuit Implementation Problem
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VLSID
2002
IEEE
207views VLSI» more  VLSID 2002»
14 years 7 months ago
Synthesis of High Performance Low Power Dynamic CMOS Circuits
This paper presents a novel approach for the synthesis of dynamic CMOS circuits using Domino and Nora styles. As these logic styles can implement only non-inverting logic, convent...
Debasis Samanta, Nishant Sinha, Ajit Pal
ICCAD
1997
IEEE
112views Hardware» more  ICCAD 1997»
13 years 11 months ago
Circuit optimization via adjoint Lagrangians
The circuit tuning problem is best approached by means of gradient-based nonlinear optimization algorithms. For large circuits, gradient computation can be the bottleneck in the o...
Andrew R. Conn, Ruud A. Haring, Chandramouli Viswe...
ASPDAC
1999
ACM
113views Hardware» more  ASPDAC 1999»
13 years 11 months ago
An Efficient Iterative Improvement Technique for VLSI Circuit Partitioning Using Hybrid Bucket Structures
In this paper, we present a fast and efficient Iterative Improvement Partitioning (IIP) technique for VLSI circuits and hybrid bucket structures on its implementation. Due to thei...
C. K. Eem, J. W. Chong
ISCAS
2003
IEEE
153views Hardware» more  ISCAS 2003»
14 years 20 days ago
A VLSI model of range-tuned neurons in the bat echolocation system
The neural computations that support bat echolocation are of great interest to both neuroscientists and engineers, due to the complex and extremely time-constrained nature of the ...
Matthew Cheely, Timothy K. Horiuchi
ISCAS
2005
IEEE
158views Hardware» more  ISCAS 2005»
14 years 1 months ago
Designing optimized pipelined global interconnects: algorithms and methodology impact
— As across-chip wire delays exceed a clock cycle, interconnect pipelining becomes essential. However, the arbitrary insertion of flip-flops can change the differentials of lat...
Vidyasagar Nookala, Sachin S. Sapatnekar