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» On the Complexity of Register Coalescing
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CGO
2003
IEEE
14 years 26 days ago
Phi-Predication for Light-Weight If-Conversion
Predicated execution can eliminate hard to predict branches and help to enable instruction level parallelism. Many current predication variants exist where the result update is co...
Weihaw Chuang, Brad Calder, Jeanne Ferrante
MST
2002
107views more  MST 2002»
13 years 7 months ago
A Comparison of Asymptotically Scalable Superscalar Processors
The poor scalability of existing superscalar processors has been of great concern to the computer engineering community. In particular, the critical-path lengths of many components...
Bradley C. Kuszmaul, Dana S. Henry, Gabriel H. Loh
DSD
2008
IEEE
79views Hardware» more  DSD 2008»
14 years 2 months ago
Digital Systems Architectures Based on On-line Checkers
In this paper, a methodology for generating VHDL descriptions of hardware checkers is presented. It is shown how the methodology can be used to generate on-line checkers of commun...
Martin Straka, Zdenek Kotásek, Jan Winter
IJWMC
2007
66views more  IJWMC 2007»
13 years 7 months ago
Grain: a stream cipher for constrained environments
Abstract. A new stream cipher, Grain, is proposed. The design targets hardware environments where gate count, power consumption and memory is very limited. It is based on two shift...
Martin Hell, Thomas Johansson, Willi Meier
MEMICS
2010
13 years 2 months ago
Instructor Selector Generation from Architecture Description
We describe an automated way to generate data for a practical LLVM instruction selector based on machine-generated description of the target architecture at register transfer leve...
Miloslav Trmac, Adam Husar, Jan Hranac, Tomas Hrus...