183 search results - page 11 / 37 » On the Impact of Caching for High Performance Packet Classif... |
IEEEPACT
2002
IEEE
14 years 1 months ago
2002
IEEE
Simultaneous Multithreading (SMT) processors achieve high processor throughput at the expense of single-thread performance. This paper investigates resource allocation policies fo...
IPPS
2007
IEEE
14 years 2 months ago
2007
IEEE
This paper presents and evaluates a strategy for integrating the Snort network intrusion detection system into a high-performance programmable Ethernet network interface card (NIC...
SERSCISA
2010
Springer
13 years 10 months ago
2010
Springer
The delay and dispersion of the packet train have been widely used in most network measurement tools. The timestamp of the packet is critical for the measurement accuracy. However...
IPPS
2005
IEEE
14 years 2 months ago
2005
IEEE
As technological process shrinks and clock rate increases, instruction caches can no longer be accessed in one cycle. Alternatives are implementing smaller caches (with higher mis...
JEC
2006
13 years 8 months ago
2006
Chip multi-processors (CMP) are rapidly emerging as an important design paradigm for both high performance and embedded processors. These machines provide an important performance...