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GLVLSI
2007
IEEE
107views VLSI» more  GLVLSI 2007»
14 years 1 months ago
Side-channel resistant system-level design flow for public-key cryptography
In this paper, we propose a new design methodology to assess the risk for side-channel attacks, more specifically timing analysis and simple power analysis, at an early design st...
Kazuo Sakiyama, Elke De Mulder, Bart Preneel, Ingr...
IFIP
2004
Springer
14 years 25 days ago
Virtual Analysis and Reduction of Side-Channel Vulnerabilities of Smartcards
This paper focuses on the usability of the PINPAS tool. The PINPAS tool is an instruction-level interpreter for smartcard assembler languages, augmented with facilities to study si...
Jerry den Hartog, Erik P. de Vink
NSDI
2008
13 years 9 months ago
Designing and Implementing Malicious Hardware
Hidden malicious circuits provide an attacker with a stealthy attack vector. As they occupy a layer below the entire software stack, malicious circuits can bypass traditional defe...
Samuel T. King, Joseph Tucek, Anthony Cozzie, Chri...
ICISC
2009
132views Cryptology» more  ICISC 2009»
13 years 5 months ago
Side-Channel Analysis of Cryptographic Software via Early-Terminating Multiplications
Abstract. The design of embedded processors demands a careful tradeoff between many conflicting objectives such as performance, silicon area and power consumption. Finding such a t...
Johann Großschädl, Elisabeth Oswald, Da...
AFRICACRYPT
2009
Springer
14 years 2 months ago
Breaking KeeLoq in a Flash: On Extracting Keys at Lightning Speed
We present the first simple power analysis (SPA) of software implementations of KeeLoq. Our attack drastically reduces the efforts required for a complete break of remote keyless...
Markus Kasper, Timo Kasper, Amir Moradi, Christof ...