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IEEEPACT
2000
IEEE
14 years 2 months ago
Instruction Scheduling for Clustered VLIW DSPs
Recent digital signal processors (DSPs) show a homogeneous VLIW-like data path architecture, which allows C compilers to generate efficient code. However, still some special rest...
Rainer Leupers
FPL
1999
Springer
147views Hardware» more  FPL 1999»
14 years 2 months ago
Synthia: Synthesis of Interacting Automata Targeting LUT-based FPGAs
This paper details the development, implementation, and results of Synthia, a system for the synthesis of Finite State Machines (FSMs) to field-programmable logic. Our approach us...
George A. Constantinides, Peter Y. K. Cheung, Wayn...
ISCA
1997
IEEE
114views Hardware» more  ISCA 1997»
14 years 2 months ago
Improving Superscalar Instruction Dispatch and Issue by Exploiting Dynamic Code Sequences
Superscalar processors currently have the potential to fetch multiple basic blocks per cycle by employing one of several recently proposed instruction fetch mechanisms. However, t...
Sriram Vajapeyam, Tulika Mitra
FCT
2007
Springer
14 years 1 months ago
Multi-dimensional Packing with Conflicts
We study the multi-dimensional version of the bin packing problem with conflicts. We are given a set of squares V = {1, 2, . . . , n} with sides s1, s2, . . . , sn [0, 1] and a co...
Leah Epstein, Asaf Levin, Rob van Stee
NGC
2000
Springer
115views Communications» more  NGC 2000»
14 years 1 months ago
Hierarchical reliable multicast
The use of proxies for local error recovery and congestion control is a scalable technique used to overcome a number of wellknown problems in Reliable Multicast (RM). The idea is ...
Athina Markopoulou, Fouad A. Tobagi