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EURODAC
1995
IEEE
138views VHDL» more  EURODAC 1995»
13 years 11 months ago
Reduced design time by load distribution with CAD framework methodology information
This paper is focused on reducing the design time in a CAD framework environment by the optimal use of resources. A user-transparent load distribution system (Framework based LOad...
Jürgen Schubert, Arno Kunzmann, Wolfgang Rose...
ICES
2010
Springer
106views Hardware» more  ICES 2010»
13 years 5 months ago
The Use of Genetic Algorithm to Reduce Power Consumption during Test Application
Abstract. In this paper it is demonstrated how two issues from the area of testing electronic components can be merged and solved by means of a genetic algorithm. The two issues ar...
Jaroslav Skarvada, Zdenek Kotásek, Josef St...
VTS
1997
IEEE
86views Hardware» more  VTS 1997»
13 years 11 months ago
Methods to reduce test application time for accumulator-based self-test
Accumulators based on addition or subtraction can be used as test pattern generators. Some circuits, however, require long test lengths if the parameters of the accumulator are no...
Albrecht P. Stroele, Frank Mayer
CEC
2003
IEEE
13 years 11 months ago
Genome-physics interaction as a new concept to reduce the number of genetic parameters in artificial evolution
This paper reports on investigations on the possible advantage of the coupling between genomes and physics of cells in artificial evolution. The idea is simple: evolution can rely ...
Peter Eggenberger Hotz
KDD
2005
ACM
122views Data Mining» more  KDD 2005»
14 years 7 months ago
Pattern lattice traversal by selective jumps
Regardless of the frequent patterns to discover, either the full frequent patterns or the condensed ones, either closed or maximal, the strategy always includes the traversal of t...
Osmar R. Zaïane, Mohammad El-Hajj