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ACSC
2004
IEEE
13 years 11 months ago
Formalization of UML Statechart Models Using Concurrent Regular Expressions
The Unified Modeling Language (UML) is widely used in the software development process for specification of system based on the object-oriented paradigm. Thought the current versi...
S. Jansamak, A. Surarerks
EUROMICRO
2000
IEEE
14 years 3 days ago
Formal Coverification of Embedded Systems Using Model Checking
The complexity of embedded systems is increasing rapidly. In consequence, new verification techniques that overcome the limitations of traditional methods and are suitable for har...
Luis Alejandro Cortés, Petru Eles, Zebo Pen...
ECRTS
1999
IEEE
14 years 8 hour ago
Timed automaton models for simple programmable logic controllers
We give timed automaton models for a class of Programmable Logic Controller (PLC) applications, that are programmed in a simple fragment of the language Instruction Lists as defin...
Angelika Mader, Hanno Wupper
ECBS
2007
IEEE
145views Hardware» more  ECBS 2007»
13 years 11 months ago
Automatic Verification and Performance Analysis of Time-Constrained SysML Activity Diagrams
We present in this paper a new approach for the automatic verification and performance analysis of SysML activity diagrams. Since timeliness is important in the design and analysi...
Yosr Jarraya, Andrei Soeanu, Mourad Debbabi, Fawzi...
ECCB
2008
IEEE
13 years 7 months ago
Temporal logic patterns for querying dynamic models of cellular interaction networks
Abstract: Models of the dynamics of cellular interaction networks have become increasingly larger in recent years. Formal verification based on model checking provides a powerful t...
Pedro T. Monteiro, Delphine Ropers, Radu Mateescu,...