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ICCAD
2006
IEEE
108views Hardware» more  ICCAD 2006»
14 years 7 months ago
Soft error reduction in combinational logic using gate resizing and flipflop selection
Soft errors in logic are emerging as a significant reliability problem for VLSI designs. This paper presents novel circuit optimization techniques to mitigate soft error rates (SE...
Rajeev R. Rao, David Blaauw, Dennis Sylvester
FPGA
2010
ACM
209views FPGA» more  FPGA 2010»
14 years 7 months ago
FPGA power reduction by guarded evaluation
Guarded evaluation is a power reduction technique that involves identifying sub-circuits (within a larger circuit) whose inputs can be held constant (guarded) at specific times d...
Chirag Ravishankar, Jason Helge Anderson
WWW
2010
ACM
14 years 6 months ago
Exploiting social context for review quality prediction
Online reviews in which users publish detailed commentary about their experiences and opinions with products, services, or events are extremely valuable to users who rely on them ...
Yue Lu, Panayiotis Tsaparas, Alexandros Ntoulas, L...
WWW
2010
ACM
14 years 6 months ago
Privacy wizards for social networking sites
Privacy is an enormous problem in online social networking sites. While sites such as Facebook allow users fine-grained control over who can see their profiles, it is difficult ...
Lujun Fang, Kristen LeFevre
ICDE
2010
IEEE
258views Database» more  ICDE 2010»
14 years 5 months ago
Anonymized Data: Generation, models, usage
Data anonymization techniques have been the subject of intense investigation in recent years, for many kinds of structured data, including tabular, item set and graph data. They e...
Graham Cormode, Divesh Srivastava
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