Sciweavers

570 search results - page 101 / 114
» On the number of zero-sum subsequences
Sort
View
DAWAK
2006
Springer
14 years 1 months ago
Extending Visual OLAP for Handling Irregular Dimensional Hierarchies
Comprehensive data analysis has become indispensable in a variety of environments. Standard OLAP (On-Line Analytical Processing) systems, designed for satisfying the reporting need...
Svetlana Mansmann, Marc H. Scholl
LCTRTS
2000
Springer
14 years 1 months ago
Approximation of Worst-Case Execution Time for Preemptive Multitasking Systems
The control system of many complex mechatronic products requires for each task the Worst Case Execution Time (WCET), which is needed for the scheduler's admission tests and su...
Matteo Corti, Roberto Brega, Thomas R. Gross
ISCA
1995
IEEE
120views Hardware» more  ISCA 1995»
14 years 1 months ago
Streamlining Data Cache Access with Fast Address Calculation
For many programs, especially integer codes, untolerated load instruction latencies account for a significant portion of total execution time. In this paper, we present the desig...
Todd M. Austin, Dionisios N. Pnevmatikatos, Gurind...
MICRO
1995
IEEE
102views Hardware» more  MICRO 1995»
14 years 1 months ago
Zero-cycle loads: microarchitecture support for reducing load latency
Untolerated load instruction latencies often have a significant impact on overall program performance. As one means of mitigating this effect, we present an aggressive hardware-b...
Todd M. Austin, Gurindar S. Sohi
ASPLOS
2010
ACM
14 years 1 months ago
Micro-pages: increasing DRAM efficiency with locality-aware data placement
Power consumption and DRAM latencies are serious concerns in modern chip-multiprocessor (CMP or multi-core) based compute systems. The management of the DRAM row buffer can signif...
Kshitij Sudan, Niladrish Chatterjee, David Nellans...